1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device having an insulating gate field effect transistor (MOSFET) isolated by isolation region, and to a method of manufacturing the same.
2. Description of the Related Art
In semiconductor devices, for example, non-volatile semiconductor memory devices, the following technique is employed in order to realize micro isolation. According to the technique, the same conductivity type impurity as a substrate is passed through STI, and introduced into the substrate under the bottom surface of the STI. By doing so, a channel stopper region is formed thereon.
FIG. 1 is a flowchart to explain the process of manufacturing a MOSFET in a conventional semiconductor device. FIG. 2A and FIG. 2B are cross-sectional views showing the manufacturing process corresponding to the flowchart of FIG. 1
The process of manufacturing the conventional semiconductor device will be briefly described below with reference to FIG. 1 and FIG. 2. As shown in FIG. 2A, shallow trench isolation (STI) 11 is formed in a surface region of a semiconductor substrate 10. A resist layer 13 having a first opening is formed on the semiconductor substrate 10 by photo engraving process (PEP). Impurity ion implantation (first-time PEP channel ion implantation (I/I)) for depression type NMOSFET threshold voltage control is carried out using the resist layer 13 as a mask.
The resist layer 13 used in the process of FIG. 2A is removed (etched). As illustrated in FIG. 2B, a resist layer 15 having several second openings 14 is newly formed on the substrate 10 by the PEP. Thereafter, impurity ion implantation (second-time PEP field ion implantation (I/I)) is carried out using the resist layer 13 as a mask. The impurity ion implantation is carried out in order to form a channel stopper region at the semiconductor substrate 10 under the bottom surface of the STI 11.
According to the conventional technique, the PEP is separately carried out to form individual resist layers used for channel and filed implantations, as seen from the foregoing explanation. For this reason, the number of times for forming and removing the resist layer by the PEP increases. In order to satisfy the needs of high density and high function of elements, several MOSFETs having different threshold voltage are formed in the same substrate. In this case, the PEP for forming individual resist layers used for channel and filed implantations must be separately carried out every MOSFET group having different threshold voltage. This is a factor of increasing the manufacture cost, in particular.
Incidentally, JPN. PAT. APPLN. KOKAI Publication No. 9-322348 discloses the following technique. According to the technique, the same conductivity type impurity as a substrate and the opposite conductivity type impurity are introduced into the substrate under the bottom surface of STI through the STI.
According to the conventional technique, the PEP is separately carried out to form individual resist layers used for channel and filed implantations, as described above. For this reason, there is conventionally a problem of increasing the manufacture cost; therefore, it is desired to solve the foregoing problem.